Multiple pin logic devices are commonly inserted into printed circuit (PC) boards so that they may be coupled to other logic devices and components to create a larger digital system. The devices and components are interconnected with a conductive line pattern that is printed onto the PC board. For each unique system design, a different number of devices may be coupled to each pin of the logic device. As a result, a circuit designer often times is unable to know the amount of capacitive loading on each pin of a logic device.
The amount of capacitive loading on an I/O pin affects the rate at which the output signal transitions. Additionally, in the case when the frequency of the output signal is high and the capacitive loading on the I/O pin is large, the output signal may overshoot the target digital high or low voltage levels. In a logic system, overshoot problems may cause many types of errors, such as erroneous clocking signals, misread data, ground bounce, positive power supply droop, and even latch-up on the I/O pins internal output circuitry or on subsequent logic stages coupled to the I/O pin.
One manner in which designers have attempted to eliminate this overshoot problem is to design logic circuits with I/O buffers having controlled slew rate output signals. One such prior art buffer design, specifically designed for eliminating overshoot problems during high-to-low output transitions, includes a PMOS pull-up device and an NMOS pull-down device. The gate of the NMOS pull-down device is coupled to a CMOS inverter that is coupled in series with a constant current source (typically the current source is an MOS device that is biased into saturation by an appropriate voltage). When the input signal to the CMOS inverter transitions high-to-low, the current source is coupled to the gate of the pull-down NMOS device (through the PMOS portion of the inverter) and charges the gate capacitance of the NMOS pull-down device with a constant current. As a result, the gate voltage on the pull-down NMOS device rises to a high voltage at a slew rate controlled by the current source while the output node correspondingly discharges at the same rate. A similar prior art design is also utilized to control the low-to-high output signal slew rate of an I/O buffer.
There are several problems associated with the above described buffer. First, the gate voltage of the pull-down NMOS device and consequently, the output voltage are not truly linear because the current source's saturation drain current and its gate-to-source voltage are not linearly related. Specifically, the saturated drain current is proportional to the gate-to-source voltage squared (I.sub.D is proportional to V.sub.GS.sup.2). As a result, the slew rate of the voltage signal on the gate of the pull-down MOS device and the output node is not linear and does not perform in a digital signal-like manner. Secondly, this buffer has an associated problem with Miller feedback capacitance, also causing non-linearity in the output signal. In addition, the current source and its associated bias voltage set the slew rate of the output signal. Consequently, the above described prior art buffer design is only effective with a specific capacitive load. To change the slew rate for a given load (or to change the load while keeping the slew rate constant), either the bias voltage or size of the current source MOS device needs to be changed which may involve IC mask changes.
Another prior art buffer designed to control the slew rate of the output voltage of a device's I/O pin replaces the NMOS pull-down device of an output buffer with a number of successively sized parallel NMOS pull-down devices. The devices are connected in a serpentine arrangement such that the devices turn-on in sequence resulting in a graded turn-on. This graded turn-on effect is due to the resistance of the serpentine interconnect line connecting all of the gates of the parallel NMOS pull-down devices and the corresponding graded voltage drops along that interconnect line. In effect, as the voltage on the serpentine interconnect line increases each of the parallel NMOS pull-down devices are successively turned on, thus controlling the slew rate of the output high-to-low transition. This buffer design also includes a mechanism to turn off all of the parallel NMOS devices quickly when the output node needs to transition high again. The turn-off mechanism includes small NMOS devices coupled to the gates of each of the parallel NMOS pull-down devices. The turn-off transistors are all turned on at once so as to turn off all of the parallel NMOS pull-down devices, quickly decoupling them from the output node. In this way, the NMOS pull-down devices are all turned off when all of the turn-off devices are simultaneously turned on. The turn-off mechanism avoids the condition in which both the pull-down and pull-up devices are on simultaneously and a short circuit current occurs between the two power supplies VDD and GND.
As with the previous prior art embodiment, this buffer is limited to providing a given slew rate for a specific capacitive load (unless major mask or design changes are made). In addition, this type of technique is not effective with silicide gate technology due to the low gate resistance characteristics of this process.
The present invention is a low power BiCMOS buffer that provides an output signal having a digitally controlled slew rate. Thus, the slew rate of the output signal may be adjusted, depending on the I/O pins load capacitance and inductance.